November 27, 2022

Breaking a quantum circuit into smaller sub-circuits

Researchers at Atos Quantum Lab, Ecole Polytechnique and Argonne National Laboratory demonstrated a recently introduced method that breaks a quantum circuit into smaller sub-circuits or fragments, and thus makes it possible to run circuits that are either too wide or too deep for a given quantum processor.

Because of rapid technological progress, quantum processors of increasing quality and size are becoming available, whether of the superconducting or of the trapped-ion type. Despite this steady improvement, noisy, intermediate-scale quantum (NISQ) computers come with intrinsic limitations in terms of the number of qubits (circuit width) and decoherence time (circuit depth) they can have. Both constraints prevent one from performing quantum algorithms that require a large number of qubits or operations.

Basing their method on tensor-network techniques, the researchers showed how to decompose a circuit with a large quantum volume into smaller sub-circuits with quantum volumes compatible with NISQ devices.

The team investigated the behavior of their method on one of IBM’s 20- qubit superconducting quantum processors with various numbers of qubits and fragments. The IBM Johannesburg quantum processor comprises superconducting transmon qubits arranged in a two-dimensional grid. The compilation and noisy simulations were performed using Argonne National Laboratory’s and Atos Quantum Laboratory’s Quantum Learning Machines.

The team built noise models that capture decoherence, readout error, and gate imperfections for this particular processor. The researchers then carried out noisy simulations of the method in order to account for the observed experimental results.

We found an agreement within 20% between the experimental and the simulated success probabilities, and they observed that recombining noisy fragments yielded overall results that can outperform the results without fragmentation.

Thus, the method makes it possible not only to perform computations for circuit sizes exceeding the chip’s size but also to obtain better success probabilities for smaller circuit sizes. It paves the way to a noise-aware optimization of this fragmentation technique.

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